SH7080 Datasheet, PDF (65/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

1.2 Block Diagram
The block diagram of this LSI is shown in figure 1.1.
SH2
CPU
UBC
AUD
*²
Section 1 Overview
L bus (Iφ)
ROM
RAM
Internal bus
controller
I bus (Bφ)
BSC
Peripheral bus
controller
DTC
DMAC
External bus
Peripheral bus (Pφ)
I/O
port
(PFC)
SCI SCIF CMT H-UDI INTC Power- WDT CPG MTU2 MTU2S POE SSU I²C2 ADC
*¹
down
mode
control
[Legend]
ROM: On-chip ROM
RAM: On-chip RAM
UBC: User break controller
AUD: Advanced user debugger
H-UDI: User debugging interface
INTC:
CPG:
WDT:
Interrupt controller
Clock pulse generator
Watchdog timer
CPU: Central processing unit
BSC: Bus state controller
DMAC: Direct memory access controller
DTC: Data transfer controller
PFC: Pin function controller
MTU2: Multi-function timer pulse unit 2
MTU2S: Multi-function timer pulse unit 2 (subset)
POE: Port output enable
SCI: Serial communication interface
SCIF: Serial communication interface with FIFO
SSU: Synchronous serial communication unit
I²C2: I²C bus interface 2
CMT: Compare match timer
ADC: A/D converter
Notes: 1. Only in F-ZTAT version
2. Only in F-ZTAT version supporting full functions of E10A
Figure 1.1 Block Diagram
Rev. 3.00 May 17, 2007 Page 7 of 1582
REJ09B0181-0300