SH7080 Datasheet, PDF (453/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value
9, 8 PR[1:0] 00
7 to 3 —
All 0
2
AE
0
1
NMIF
0
R/W Description
R/W Priority Mode 1, 0
Select the priority level between channels when there are
transfer requests for multiple channels simultaneously.
00: CH0 > CH1 > CH2 > CH3
01: CH0 > CH2 > CH3 > CH1
10: Setting prohibited
11: Round-robin mode
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/(W)* Address Error Flag
Indicates that an address error occurred during DMA
transfer. If this bit is set, DMA transfer is disabled even if
the DE bit in CHCR and the DME bit in DMAOR are set to
1. This bit can only be cleared by writing 0 after reading
1.
0: No DMAC address error
[Clearing condition]
• Writing AE = 0 after AE = 1 read
1: DMAC address error occurs
R/(W)* NMI Flag
Indicates that an NMI interrupt occurred. If this bit is set,
DMA transfer is disabled even if the DE bit in CHCR and
the DME bit in DMAOR are set to 1. This bit can only be
cleared by writing 0 after reading 1.
When the NMI is input, the DMA transfer in progress can
be done in one transfer unit. When the DMAC is not in
operational, the NMIF bit is set to 1 even if the NMI
interrupt was input.
0: No NMI interrupt
[Clearing condition]
• Writing NMIF = 0 after NMIF = 1 read
1: NMI interrupt occurs
Rev. 3.00 May 17, 2007 Page 395 of 1582
REJ09B0181-0300