SH7080 Datasheet, PDF (264/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Data Transfer Controller (DTC)
The number of execution cycles is calculated from the formula below. Note that Σ means the sum
of cycles for all transfers initiated by one activation event (the number of 1-valued CHNE bits in
transfer information plus 1).
Number of execution cycles = I ^• S_I + Σ (J ^• S_J + K ^• S_K + L ^• S_L + M ^• S_M) + N ^• S_N
8.5.9 DTC Bus Release Timing
The DTC requests the bus mastership to the bus arbiter when an activation request occurs. The
DTC releases the bus after a vector read, NOP cycle generation after a vector read, transfer
information read, a single data transfer, or transfer information writeback. The DTC does not
release the bus mastership during transfer information read, single data transfer, or transfer
information writeback.
The bus release timing can be specified through the bus function extending register (BSCEHR).
For details see section 9.4.8, Bus Function Extending Register (BSCEHR). The difference in bus
release timing according to the register setting is summarized in table 8.11. Settings other than
settings 1 to 5 are not allowed. The setting must not be changed while the DTC is active.
Figure 8.16 is a timing chart showing an example of bus release timing.
Rev. 3.00 May 17, 2007 Page 206 of 1582
REJ09B0181-0300