SH7080 Datasheet, PDF (411/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

CK
FRAME
D31 to D0
A25 to A0
CS6
RDWR
WAIT
BS
DACKn*
Section 9 Bus State Controller (BSC)
Tm1
Tmd1w
Tmd1w
Tmd1
A
D
Note: * The waveform for DACKn is when active low is specified.
Figure 9.45 Burst MPX Space Access Timing
(Single Write, Software Wait 1, Hardware Wait 1)
Rev. 3.00 May 17, 2007 Page 353 of 1582
REJ09B0181-0300