SH7080 Datasheet, PDF (418/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Table 9.30 Minimum Number of Idle Cycles between Access Cycles during DMAC Dual
Address Mode and DTC Transfer for the Normal Space Interface
BSC Register Setting
When Access Size is
Less than Bus Width
When Access Size Exceeds Bus Width
CSnWCR. CSnBCR Read to
WM Setting Idle Setting Write
Write to
Read
Continuous Read to
Read*¹
Write*²
Continuous Write to
Write*¹
Read*²
1
0
2
0
0
2
0
0
0
0
2
1
1
2
1
1
1
1
2
1
1
2
1
1
0
1
2
1
1
2
1
1
1
2
2
2
2
2
2
2
0
2
2
2
2
2
2
2
1
4
4
4
4
4
4
4
0
4
4
4
4
4
4
4
Notes: DMAC and DTC are driven by Bφ. The minimum number of idle cycles is not affected by
changing a clock ratio.
1. Minimum number of idle cycles between the word access to address 0 and the word
access to address 2 in the 32-bit access with a 16-bit bus width,
minimum number of idle cycles between the byte access to address 0 and the byte
access to address 1 in the 16-bit access with an 8-bit bus width,
minimum number of idle cycles between the byte accesses to address 0, to address 1,
to address 2, and to address 3 in the 32-bit access with an 8-bit bus width, and
minimum number of idle cycles between consecutive accesses in 16-byte transfer.
2. Other than the above cases.
Rev. 3.00 May 17, 2007 Page 360 of 1582
REJ09B0181-0300