SH7080 Datasheet, PDF (1624/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
Page Revision (See Manual for Details)
23.5.2 User Program Mode
1264 Added
(3) Erasing Procedure in User Program Mode
The frequency division ratio of an internal clock (Iφ), a
bus clock (Bφ), and a peripheral clock (Pφ) is specified
as ×1/4 (initial value) by the frequency control register
(FRQCR).
After the programming/erasing program has been
downloaded and the SCO bit is cleared to 0, the setting
of the frequency control register (FRQCR) can be
changed to the desired value.
Figure 23.13 Sample Procedure of 1265
Repeating RAM Emulation,
Erasing, and Programming
(Overview)
Amended
Initialize erasing program
Set FTDAR to H'04
(Specify H'FFFFB000 as
download destination)
23.8.3 Other Notes
Section 24 Mask ROM
25.1.3 Initial Values in RAM
Download programming
program
Initialize programming
program
1
1281 Amended
1. Download time of on-chip program
The programming program that includes the
initialization routine and the erasing program that
includes the initialization routine are each 3 kbytes
or less. Accordingly, when the CPU clock frequency
is 20 MHz, the download for each program takes
approximately 10 ms at maximum.
1282 Added
5. Note on programming the product having a 256-
Kbyte user MAT
If an attempt is made to program the product having
a 256-Kbyte user MAT with more than 256 Kbytes,
data programmed after the first 256 Kbytes are not
guaranteed.
1323, Newly added.
1324
1326 Added
Rev. 3.00 May 17, 2007 Page 1566 of 1582
REJ09B0181-0300