SH7080 Datasheet, PDF (1625/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
Page Revision (See Manual for Details)
26.3.6 Standby Control Register 6 1336 Added
(STBCR6)
Bit Bit Name Description
7 AUDSRST AUD Software Reset
……
0: Shifts to the AUD reset state
1: Clears the AUD reset
When setting this bit to 1, the MSTP25 bit in
STBCR5 should be 0.
26.4.2 Canceling Sleep Mode
1338 Added
Sleep mode is canceled by a reset.
Do not cancel sleep mode with an interrupt.
26.8.3 Executing the SLEEP
Instruction
1343 Added
27.1 Register Address Table (In 1346 Item of "Connected Bus Width" added.
the Order from Lower Addresses) to
1360
27.2 Register Bit List
1372 Amended
Bit
Bit
Bit
Bit
Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4
SSCR2



TENDSTS
27.3 Register States in Each
Operating Mode
1402 Amended
Register
Power- Manual
Abbreviation on reset reset
Deep
Software Software Module
Standby Standby Standby Sleep
Module
BRSR*⁴
BRDR*⁴
BETR*⁴
Initialized Initialized Retained Initialized Initialized Retained UBC
Initialized Initialized Retained Initialized Initialized Retained
Initialized Retained Retained Initialized Initialized Retained
1402 ^Added
Notes: 4. Only in F-ZTAT version.
Rev. 3.00 May 17, 2007 Page 1567 of 1582
REJ09B0181-0300