SH7080 Datasheet, PDF (397/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
CK
Address
T1 Tw Tw TB2 Twb TB2 Twb TB2 Twb T2
CS
RDWR
RD
D31 to D0
WAIT
BS
DACK
Figure 9.31 Burst ROM (Clock Asynchronous) Access
(Bus Width = 32 Bits, 16 byte Transfer (Number of Burst = 4),
Access Wait for the 1st time = 2, Access Wait for 2nd Time and after = 1)
9.5.8 SRAM Interface with Byte Selection
The SRAM interface with byte selection is a memory interface which outputs a byte-selection pin
(WRxx) in a read/write bus cycle. This interface has 16-bit data pins and accesses SRAMs having
upper and lower byte-selection pins, such as UB and LB.
When the BAS bit in CSnWCR is cleared to 0 (initial value), the write access timing of the SRAM
interface with byte selection is the same as that for the normal space interface. While in read
access of the SRAM interface with byte selection, the byte-selection signal is output from the
WRxx pin, which is different from that for the normal space interface. The basic access timing is
shown in figure 9.32. In write access, data is written to memory according to the timing of the
byte-selection pin (WRxx). For details, refer to the Data Sheet for the corresponding memory.
If the BAS bit in CSnWCR is set to 1, the WRxx pin and RDWR pin timings change. Figure 9.33
shows the basic access timing. In write access, data is written to memory according to the timing
of the write enable pin (RDWR). The data hold timing from RDWR negation to data write must be
acquired by setting the HW1 and HW0 bits in the CSnWCR register. Figure 9.34 shows the access
timing when a software wait is specified.
Rev. 3.00 May 17, 2007 Page 339 of 1582
REJ09B0181-0300