SH7080 Datasheet, PDF (448/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Descriptions
17
AM
0
R/W Acknowledge Mode
Selects whether DACK is output in data read cycle or in
data write cycle in dual address mode.
In single address mode, DACK is always output
regardless of the specification by this bit.
0: DACK output in read cycle (dual address mode)
1: DACK output in write cycle (dual address mode)
16
AL
0
R/W Acknowledge Level
Specifies whether the DACK signal output is high active
or low active.
0: Low-active output of DACK
1: High-active output of DACK
15, 14 DM[1:0] 00
R/W Destination Address Mode 1, 0
Specify whether the DMA destination address is
incremented, decremented, or left fixed. (In single
address mode, the DM1 and DM0 bits are ignored when
data is transferred to an external device with DACK.)
00: Fixed destination address (setting prohibited in 16-
byte transfer)
01: Destination address is incremented (+1 in byte-unit
transfer, +2 in word-unit transfer, +4 in longword-unit
transfer, +16 in 16-byte transfer)
10: Destination address is decremented (–1 in byte-unit
transfer, –2 in word-unit transfer, –4 in longword-unit
transfer; setting prohibited in 16-byte transfer)
11: Setting prohibited
13, 12 SM[1:0] 00
R/W Source Address Mode 1, 0
Specify whether the DMA source address is incremented,
decremented, or left fixed. (In single address mode, SM1
and SM0 bits are ignored when data is transferred from
an external device with DACK.)
00: Fixed source address (setting prohibited in 16-byte
transfer)
01: Source address is incremented (+1 in byte-unit
transfer, +2 in word-unit transfer, +4 in longword-unit
transfer, +16 in 16-byte transfer)
10: Source address is decremented (–1 in byte-unit
transfer, –2 in word-unit transfer, –4 in longword-unit
transfer; setting prohibited in 16-byte transfer)
11: Setting prohibited
Rev. 3.00 May 17, 2007 Page 390 of 1582
REJ09B0181-0300