SH7080 Datasheet, PDF (920/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 17 Synchronous Serial Communication Unit (SSU)
17.3 Register Descriptions
The SSU has the following registers. For details on the addresses of these registers and the states
of these registers in each processing state, see section 27, List of Registers.
Table 17.2 Register Configuration
Register Name
SS control register H
SS control register L
SS mode register
SS enable register
SS status register
SS control register 2
SS transmit data register 0
SS transmit data register 1
SS transmit data register 2
SS transmit data register 3
SS receive data register 0
SS receive data register 1
SS receive data register 2
SS receive data register 3
Abbrevia-
tion
R/W Initial value Address
Access Size
SSCRH
R/W H'0D
H'FFFFCD00 8, 16
SSCRL
R/W H'00
H'FFFFCD01 8
SSMR
R/W H'00
H'FFFFCD02 8, 16
SSER
R/W H'00
H'FFFFCD03 8
SSSR
R/W H'04
H'FFFFCD04 8, 16
SSCR2
R/W H'00
H'FFFFCD05 8
SSTDR0 R/W H'00
H'FFFFCD06 8, 16
SSTDR1 R/W H'00
H'FFFFCD07 8
SSTDR2 R/W H'00
H'FFFFCD08 8, 16
SSTDR3 R/W H'00
H'FFFFCD09 8
SSRDR0 R
H'00
H'FFFFCD0A 8, 16
SSRDR1 R
H'00
H'FFFFCD0B 8
SSRDR2 R
H'00
H'FFFFCD0C 8, 16
SSRDR3 R
H'00
H'FFFFCD0D 8
Rev. 3.00 May 17, 2007 Page 862 of 1582
REJ09B0181-0300