SH7080 Datasheet, PDF (1286/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 23 Flash Memory
23.4.2 Programming/Erasing Interface Registers
The programming/erasing interface registers are as described below. They are all 8-bit registers
that can be accessed in bytes.
(1) Flash Code Control and Status Register (FCCS)
FCCS is configured by bits which request the monitor of the FWE pin state and error
occurrence during programming or erasing flash memory and the download of the on-chip
program.
Bit: 7
6
5
4
3
2
1
0
FWE MAT
- FLER -
-
- SCO
Initial value: 1/0 1/0 0
0
0
0
0
0
R/W: R
R
R
R
R
R
R (R)/W
Initial
Bit
Bit Name Value R/W Description
7
FWE
1/0
R
Flash Programming Enable
Monitors the level which is input to the FWE pin that
performs hardware protection of the flash memory
programming or erasing. The initial value is 0 or 1
according to the FWE pin state.
0: When the FWE pin goes low (in hardware protection
state)
1: When the FWE pin goes high
6
MAT
1/0
R
MAT Bit
Indicates whether the user MAT or user boot MAT is
selected.
0: User MAT is selected
1: User boot MAT is selected
5

0
R
Reserved
This bit is always read as 0. The write value should always
be 0.
Rev. 3.00 May 17, 2007 Page 1228 of 1582
REJ09B0181-0300