SH7080 Datasheet, PDF (462/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
Figure 10.4 shows how the priority changes when channel 0 and channel 3 transfers are requested
simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC
operates as follows:
1. Transfer requests are generated simultaneously to channels 0 and 3.
2. Channel 0 has a higher priority, so the channel 0 transfer begins first (channel 3 waits for
transfer).
3. A channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both
waiting)
4. When the channel 0 transfer ends, channel 0 becomes lowest priority.
5. At this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins
(channel 3 waits for transfer).
6. When the channel 1 transfer ends, channel 1 becomes lowest priority.
7. The channel 3 transfer begins.
8. When the channel 3 transfer ends, channels 3 and 2 shift downward in priority so that channel
3 becomes the lowest priority.
Transfer request Waiting channel(s) DMAC operation
Channel priority
(1) Channels 0 and 3
(3) Channel 1
(2) Channel 0 transfer
3
start
1,3 (4) Channel 0 transfer
ends
0>1>2>3
Priority order
changes
1>2>3>0
(5) Channel 1 transfer
starts
Priority order
3 (6) Channel 1 transfer ^changes
2>3>0>1
ends
(7) Channel 3 transfer
starts
None
(8) Channel 3 transfer
ends
Priority order
changes
0>1>2>3
Figure 10.4 Changes in Channel Priority in Round-Robin Mode
Rev. 3.00 May 17, 2007 Page 404 of 1582
REJ09B0181-0300