SH7080 Datasheet, PDF (241/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Data Transfer Controller (DTC)
8.2.9 DTC Vector Base Register (DTCVBR)
DTCVBR is a 32-bit register that specifies the base address for vector table address calculation.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W Description
31 to 12
11 to 0 
All 0
R/W Bits 11 to 0 are always read as 0. The write value should
All 0
R
always be 0.
8.2.10 Bus Function Extending Register (BSCEHR)
BSCEHR is a 16-bit register that specifies the timing of bus release by the DTC and other
functions. This register can be used to give higher priority to the transfer by the DTC and
configure the functions that can reduce the number of cycles over which the DTC is active. For
more details, see section 9.4.8, Bus Function Extending Register (BSCEHR).
Rev. 3.00 May 17, 2007 Page 183 of 1582
REJ09B0181-0300