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| SH7080 Datasheet, PDF (377/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family | |||
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CK
A25 to A0
A12/A11*1
CSn
RASL, RASU
CASL, CASU
RDWR
DQMxx
D31 to D0
BS
DACKn*2
Section 9 Bus State Controller (BSC)
Tw
Td1
Td2
Td3
Td4
Tr
Trw
Tc1
Tc2
Tc3
Tc4
Tde
Tap
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.18 Burst Read Wait Specification Timing (Auto-Precharge)
Rev. 3.00 May 17, 2007 Page 319 of 1582
REJ09B0181-0300
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