SH7080 Datasheet, PDF (331/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Bit
Bit Name
15 to 12 
11
RFSH
10
RMODE
9

8
BACTV
7 to 5 
Initial
Value R/W
All 0 R
0
R/W
0
R/W
0
R
0
R/W
All 0 R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Refresh Control
Specifies whether or not the refresh operation of
SDRAM is performed.
0: No refresh
1: Refresh
Refresh Control
Specifies whether to perform auto-refresh or self-
refresh when the RFSH bit is 1. When the RFSH bit is 1
and this bit is 1, self-refresh starts immediately. When
the RFSH bit is 1 and this bit is 0, auto-refresh starts
according to the contents that are set in RTCSR,
RTCNT, and RTCOR.
0: Auto-refresh is performed
1: Self-refresh is performed
Reserved
This bit is always read as 0. The write value should
always be 0.
Bank Active Mode
Specifies to access whether in auto-precharge mode
(using READA and WRITA commands) or in bank
active mode (using READ and WRIT commands).
0: Auto-precharge mode (using READA and WRITA
commands)
1: Bank active mode (using READ and WRIT
commands)
Note: Bank active mode can be used only for the area
3. The bus width can be set as 16 or 32 bits.
When both the area 2 and area 3 are set to
SDRAM, specify auto-precharge mode.
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 May 17, 2007 Page 273 of 1582
REJ09B0181-0300