SH7080 Datasheet, PDF (1098/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 21 Pin Function Controller (PFC)
21.1.1 Port A I/O Register L, H (PAIORL, PAIORH)
PAIORL and PAIORH are 16-bit readable/writable registers that are used to set the pins on port A
as inputs or outputs. Bits PA29IOR to PA0IOR correspond to pins PA29 to PA0 (names of
multiplexed pins are here given as port names and pin numbers alone). PAIORL is enabled when
the port A pins are functioning as general-purpose inputs/outputs (PA15 to PA0). In other states,
PAIORL is disabled. PAIORH is enabled when the port A pins are functioning as general-purpose
input/output (PA29 to PA16). In other states, PAIORH is disabled.
A given pin on port A will be an output pin if the corresponding bit in PAIORH or PAIORL is set
to 1, and an input pin if the bit is cleared to 0.
However, bits 13 to 0 of PAIORH, and bits 11, 6, and 2 to 0 of PAIORL are disabled in SH7083.
Bits 13 to 2 of PAIORH are disabled in SH7084. Bits 13 to 10 of PAIORH are disabled in
SH7085.
Bits 15 and 14 of PAIORH are reserved. These bits are always read as 0. The write value should
always be 0.
The initial values of PAIORL and PAIORH are H'0000, respectively.
• Port A I/O Register H (PAIORH)
Bit: 15
-
Initial value: 0
R/W: R
14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
PA29 PA28 PA27 PA26 PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16
IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
• Port A I/O Register L (PAIORL)
Bit: 15
PA15
IOR
Initial value: 0
R/W: R/W
14
PA14
IOR
0
R/W
13
PA13
IOR
0
R/W
12
PA12
IOR
0
R/W
11
PA11
IOR
0
R/W
10
PA10
IOR
0
R/W
9
PA9
IOR
0
R/W
8
PA8
IOR
0
R/W
7
PA7
IOR
0
R/W
6
PA6
IOR
0
R/W
5
PA5
IOR
0
R/W
4
PA4
IOR
0
R/W
3
PA3
IOR
0
R/W
2
PA2
IOR
0
R/W
1
PA1
IOR
0
R/W
0
PA0
IOR
0
R/W
Rev. 3.00 May 17, 2007 Page 1040 of 1582
REJ09B0181-0300