SH7080 Datasheet, PDF (390/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
CK
A25 to A0
A12/A11*¹
CSn
RASL, RASU
CASL, CASU
RDWR
DQMxx
D31 to D0
BS
DACKn*²
Tp
Tpw
Trr
Trc
Trc
Trc
Hi-z
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.28 Auto-Refresh Timing
2. Self-refreshing
Self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses
are generated within SDRAM. Self-refreshing is activated by setting both the RMODE bit and
the RFSH bit in SDCR to 1. After starting the self-refreshing, PALL command is issued in the
Tp cycle after the completion of the precharging bank. A SELF command is then issued after
inserting idle cycles of which number is specified by the WTRP[1:0] bits in CS3WCR.
SDRAM cannot be accessed while in the self-refresh state. Self-refresh mode is cleared by
clearing the RMODE bit to 0. After self-refresh mode has been cleared, command issuance is
disabled for the number of cycles specified by the WTRC[1:0] bits in CS3WCR.
Self-refresh timing is shown in figure 9.29. After self-refreshing is cleared, settings must be
made so that auto-refreshing is performed at the correct intervals. When self-refreshing is
activated from the state in which auto-refreshing is set, auto-refreshing is restarted if the RFSH
bit is set to 1 and the RMODE bit is cleared to 0 when self-refresh mode is cleared. If the
transition from clearing of self-refresh mode to the start of auto-refreshing takes time, making
the RTCNT value 1 less than the RTCOR value will enable auto-refreshing to be started
immediately.
Rev. 3.00 May 17, 2007 Page 332 of 1582
REJ09B0181-0300