SH7080 Datasheet, PDF (400/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Th
T1
Tw
T2
Tf
CK
A29 to A0
CSn
WRxx
RDWR
Read
RD
D31 to D0
RDWR
Write
RD
D31 to D0
BS
High
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.34 Byte Selection SRAM Wait Timing
(BAS = 1, SW[1:0] = 01, WR[3:0] = 0001, HW[1:0] = 01)
Rev. 3.00 May 17, 2007 Page 342 of 1582
REJ09B0181-0300