SH7080 Datasheet, PDF (1629/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
Table 28.8 Bus Timing
Page Revision (See Manual for Details)
1418
to
1420
Amended
Item
Address delay time 1
Address delay time 2
BS delay time
CS delay time
Read write delay time
Read strobe delay time
Read data setup time 1
Read data setup time 2
Read data setup time 3
Read data access time
Symbol Min.
Max.
t
AD1
t
AD2
t
BSD
t
CSD
t
RWD
t
RSD
t
RDS1
t
RDS2
t
RDS3
t *2
ACC
1
18
1/2t + 1
Bcyc
—
1/2t +18
Bcyc
18
1
18
1
18
1/2t + 1
Bcyc
1/2t + 18
Bcyc
19
1/2t + 18
Bcyc
—
—
1/2t + 18 —
Bcyc
t×
—
Bcyc
(n +1.5) − 33
Access time from read strobe t_OE*²
t×
—
Bcyc
(n + 1) − 31
Write strobe delay time 1
t
WSD1
1/2t + 1
Bcyc
1/2t + 18
Bcyc
Write strobe delay time 2
t_WSD2
—
18
Write data delay time 1
t_WDD1
—
18
Write data delay time 2
t_WDD2
—
18
WAIT setup time
WAIT hold time
RAS delay time
t
WTS
t
WTH
t
RASD
1/2t + 17 —
Bcyc
1/2t + 7 —
Bcyc
1
18
CAS delay time
t
1
18
CASD
DQM delay time
t
1
18
DQMD
CKE delay time
t
1
18
CKED
AH delay time
t
1/2t + 1 1/2t + 18
AHD
Bcyc
Bcyc
Multiplexed address delay time t
—
18
MAD
DACK, TEND delay time
t
1
18
DACD
FRAME delay time
t_FMD
1
18
ICIORD delay time
t_ICRSD
1/2t_Bcyc + 1
1/2t_Bcyc + 18
ICIOWR delay time
t_ICWSD
1/2t_Bcyc + 1
1/2t_Bcyc + 18
Notes: 3. The operation of the F-ZTAT version supporting full functions
of E10A is guaranteed between temperatures of 0 to +50°C.
Rev. 3.00 May 17, 2007 Page 1571 of 1582
REJ09B0181-0300