SH7080 Datasheet, PDF (1621/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
21.1.9 Port E I/O Registers L, H
(PEIORL, PEIORH)
21.1.10 Port E Control Registers
L1 to L4, H1, H2 (PECRL1 to
PECRL4, PECRH1, PECRH2)
SH7085:
• Port E Control Register L1
(PECRL1)
Page Revision (See Manual for Details)
1125 Deleted
…. PEIORL is enabled when the port E pins are
functioning as general-purpose inputs/outputs (PE15 to
PE0), the SCK pin is functioning as inputs/outputs of
SCI/SCIF, and the TIOC pin is functioning as
inputs/outputs of MTU2. In other states, PEIORL is
disabled.
1146 Deleted
Bit Bit Name Description
10 PE2MD2 PE2 Mode
9 PE2MD1 Select the function of the
8 PE2MD0 ^{PE2/DREQ1/TIOC0C/AUDRST pin. Fixed to}
AUDRST input when using the AUD function of
the E10A.
6 PE1MD2 PE1 Mode
5 PE1MD1 Select the function of the
4 PE1MD0 ^{PE1/TEND0/TIOC0B/AUDMD pin. Fixed to}
AUDMD input when using the AUD function of
the E10A.
SH7086:
• Port E Control Register L1
(PECRL1)
1155, Deleted
1156 _{Bit Bit Name Description}
10 PE2MD2 PE2 Mode
9 PE2MD1 Select the function of the
8 PE2MD0 ^{PE2/DREQ1/TIOC0C/AUDRST pin. Fixed to}
AUDRST input when using the AUD function of
the E10A.
6 PE1MD2 PE1 Mode
5 PE1MD1 Select the function of the
4 PE1MD0 ^{PE1/TEND0/TIOC0B/AUDMD pin. Fixed to}
AUDMD input when using the AUD function of
the E10A.
Rev. 3.00 May 17, 2007 Page 1563 of 1582
REJ09B0181-0300