SH7080 Datasheet, PDF (665/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is
set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare
match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The
MTU2 has 21 input capture/compare match interrupts, six for channel 0, four each for channels 3
and 4, two each for channels 1 and 2, and three for channel 5. The TGFE_0 and TGFF_0 flags in
channel 0 are not set by the occurrence of an input capture.
Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the
TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt
request is cleared by clearing the TCFV flag to 0. The MTU2 has five overflow interrupts, one for
each channel.
Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the
TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt
request is cleared by clearing the TCFU flag to 0. The MTU2 has two underflow interrupts, one
each for channels 1 and 2.
11.5.2 DTC/DMAC Activation
DTC Activation: The DTC can be activated by the TGR input capture/compare match interrupt in
each channel or the overflow interrupt in channel 4. For details, see section 8, Data Transfer
Controller (DTC).
A total of 20 MTU2 input capture/compare match interrupts and overflow interrupts can be used
as DTC activation sources, four each for channels 0 and 3, two each for channels 1 and 2, five for
channel 4, and three for channel 5.
DMAC Activation: The DMAC can be activated by the TGRA input capture/compare match
interrupt in each channel. For details, see section 10, Direct Memory Access Controller (DMAC).
In the MTU2, a total of five TGRA input capture/compare match interrupts can be used as DMAC
activation sources, one each for channels 0 to 4.
When the DMAC is activated by the MTU2, the activation source is cleared at the point the
DMAC requests the internal bus mastership. Therefore, the request for DMAC transfer may be
kept pending for a certain period even after the activation source is cleared depending on the
internal bus state. To initiate burst transfer by the DMAC using an MTU2 interrupt, setting of the
bus function extending register (BSCEHR) is necessary. For details, see section 9.4.8, Bus
Function Extending Register (BSCEHR).
Rev. 3.00 May 17, 2007 Page 607 of 1582
REJ09B0181-0300