SH7080 Datasheet, PDF (87/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 2 CPU
2.3.3 Immediate Data Formats
Immediate data of eight bits is placed in the instruction code.
For the MOV, ADD, and CMP/EQ instructions, the immediate data is sign-extended to longword
and then calculated. For the TST, AND, OR, and XOR instructions, the immediate data is zero-
extended to longword and then calculated. Thus, if the immediate data is used for the AND
instruction, the upper 24 bits in the destination register are always cleared.
The immediate data of word or longword is not placed in the instruction code. It is placed in a
table in memory. The table in memory is accessed by the MOV immediate data instruction in PC
relative addressing mode with displacement.
2.4 Features of Instructions
2.4.1 RISC Type
The instructions are RISC-type instructions with the following features:
Fixed 16-Bit Length: All instructions have a fixed length of 16 bits. This improves program code
efficiency.
One Instruction per Cycle: Since pipelining is used, basic instructions can be executed in one
cycle.
Data Size: The basic data size for operations is longword. Byte, word, or longword can be
selected as the memory access size. Byte or word data in memory is sign-extended to longword
and then calculated. Immediate data is sign-extended to longword for arithmetic operations or
zero-extended to longword size for logical operations.
Table 2.2 Word Data Sign Extension
CPU in this LSI
Description
MOV.W @(disp,PC),R1
ADD
R1,R0
........
.DATA.W H'1234
Sign-extended to 32 bits, R1
becomes H'00001234, and is
then operated on by the ADD
instruction.
Note: * Immediate data is accessed by @(disp,PC).
Example of Other CPUs
ADD.W #H'1234,R0
Rev. 3.00 May 17, 2007 Page 29 of 1582
REJ09B0181-0300