SH7080 Datasheet, PDF (1600/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
4.5 Changing Frequency
Table 5.5 Reset Status
Page Revision (See Manual for Details)
81 Amended
3. …..When using the MTU2S clock and MTU2 clock,
specify the frequencies to satisfy the following
condition: internal clock (Iφ) ≥ MTU2S clock (MIφ) ≥
MTU2 clock (MPφ) ≥ peripheral clock (Pφ) and bus
clock (Bφ) ≥ MTU2 clock (MPφ).
Code to rewrite values of FRQCR should be
executed in the on-chip ROM or on-chip RAM.
4. After an instruction to rewrite FRQCR has been
issued, the actual clock frequencies will change after
(1 to 24n) cyc + 11Bφ + 7Pφ.
n: Division ratio specified by the BFC bit in FRQCR
(1, 1/2, 1/3, 1/4, or 1/8)
cyc: Clock obtained by dividing EXTAL by 8 with the
PLL.
Note: (1 to 24n) depends on the internal state.
91 Amended
Internal State
Type
POE, PFC, I/O Port
Power-on reset
Initialized
Initialized
Manual reset
Not initialized
Section 7 User Break Controller
(UBC)
135 Added
….Break conditions that can be set in the UBC are
instruction fetch or data read/write access, data size,
data contents, address value, and stop timing in the
case of instruction fetch.
For the mask ROM version, only the L-bus instruction-
fetch address break (2 channels) is available.
7.1 Features
135 Amended
5. Four pairs of branch source/destination buffers
(eight pairs for F-ZTAT version supporting full
functions of E10A).
Table 7.2 Register Configuration 138 Note added.
Note: * Only in F-ZTAT version
Rev. 3.00 May 17, 2007 Page 1542 of 1582
REJ09B0181-0300