SH7080 Datasheet, PDF (306/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
10, 9 BSZ[1:0] 11*
R/W Data Bus Size Specification
Specify the data bus sizes of spaces.
00: Setting prohibited
01: 8-bit size
10: 16-bit size
11: 32-bit size
Bus width determined by the address when
MPX-I/O is used
Notes: 1. When MPX-I/O is selected for area 5, setting
these bits to 11 enables the bus width (8 bits
or 16 bits) to be determined by the address
according to the SZSEL bit setting in
CS5WCR.
2. When the on-chip ROM is disabled, the data
bus width in area 0 is specified through
external input pins. The BSZ1 and BSZ0 bit
setting in CS0BCR is ignored.
3. When burst MPX-I/O is selected for area 6,
only 32-bit size can be selected for the bus
width.
4. When PCMCIA is selected for area 5 or 6, 8-
bit or 16-bit size can be selected for the bus
width.
5. When SDRAM is selected for area 2 or 3,
16-bit or 32-bit size can be selected for the
bus width.
8 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Note: * When the on-chip ROM is disabled, CS0BCR samples the value input through the MD0
and MD1 external pins that specify the bus width when a power-on reset is performed.
Rev. 3.00 May 17, 2007 Page 248 of 1582
REJ09B0181-0300