SH7080 Datasheet, PDF (818/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 15 Serial Communication Interface (SCI)
Transmitting Serial Data (Asynchronous Mode):
Figure 15.4 shows a sample flowchart for serial transmission.
Use the following procedure for serial data transmission after enabling the SCI for transmission.
Start of transmission
Read TDRE flag in SCSSR
No
TDRE = 1?
Yes
Write transmit data in SCTDR
and clear TDRE bit in SCSSR to 0
No
All data transmitted?
Yes
Read TEND flag in SCSSR
No
TEND = 1?
Yes
No
Break output?
Yes
Clear SPB0DT to 0 and
set SPB0IO to 1
Clear TE bit in SCSCR to 0
[1] SCI status check and transmit data
write:
Read SCSSR and check that the
TDRE flag is set to 1, then write
transmit data to SCTDR, and clear
the TDRE flag to 0.
[2] Serial transmission continuation
procedure:
To continue serial transmission, read
1 from the TDRE flag to confirm that
writing is possible, then write data to
SCTDR, and then clear the TDRE
flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DMAC or
DTC is activated by a transmit data
empty interrupt (TXI) request, and
data is written to SCTDR.
[3] Break output at the end of serial
transmission:
To output a break in serial
transmission, clear the SPB0DT bit to
0 and set the SPB0IO bit to 1 in
SCSPTR, then clear the TE bit in
SCSCR to 0.
End of transmission
Figure 15.4 Sample Flowchart for Transmitting Serial Data
Rev. 3.00 May 17, 2007 Page 760 of 1582
REJ09B0181-0300