SH7080 Datasheet, PDF (313/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
10 to 7 WR[3:0] 1010 R/W Number of Wait Cycles in Read Access
Specify the number of wait cycles required for read
access.
0000: 0 cycles
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
6
WM
0
R/W External Wait Mask Specification
Specifies whether or not the external wait input is valid.
The specification by this bit is valid even when the
number of access wait cycles is 0.
0: External wait is valid
1: External wait is ignored
5 to 2 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 May 17, 2007 Page 255 of 1582
REJ09B0181-0300