SH7080 Datasheet, PDF (852/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.4 Transmit FIFO Data Register (SCFTDR)
SCFTDR is a 16-stage 8-bit FIFO register that stores data for serial transmission. When the SCIF
detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in the
SCFTDR into SCTSR and starts serial transmission. Continuous serial transmission is performed
until there is no transmit data left in SCFTDR. SCFTDR can always be written to by the CPU.
When SCFTDR is full of transmit data (16 bytes), no more data can be written. If writing of new
data is attempted, the data is ignored.
Bit: 7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
R/W: W W W W W W W W
Bit
7 to 0
Bit Name
Initial
value
R/W
Undefined W
Description
FIFO for transmits serial data
16.3.5 Serial Mode Register (SCSMR)
SCSMR is a 16-bit register that specifies the SCIF serial communication format and selects the
clock source for the baud rate generator.
The CPU can always read and write to SCSMR.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
C/A CHR PE O/E STOP -
CKS[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R R/W R/W
Bit
15 to 8
Bit Name

Initial
value
All 0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 May 17, 2007 Page 794 of 1582
REJ09B0181-0300