SH7080 Datasheet, PDF (44/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Figure 28.32 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Bank Active Mode: ACT + READ Commands, CAS Latency 2,
WTRCD = 0 Cycle) ............................................................................................ 1442
Figure 28.33 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Bank Active Mode: READ Command, Same Row Address, CAS Latency 2,
WTRCD = 0 Cycle) .............................................................................................. 1443
Figure 28.34 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Bank Active Mode: PRE + ACT + READ Commands,
Different Row Addresses, CAS Latency 2, WTRCD = 0 Cycle)....................... 1444
Figure 28.35 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
(Bank Active Mode: ACT + WRITE Commands, WTRCD = 0 Cycle,
TRWL = 0 Cycle)................................................................................................ 1445
Figure 28.36 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
(Bank Active Mode: WRITE Command, Same Row Address,
WTRCD = 0 Cycle, TRWL = 0 Cycle).............................................................. 1446
Figure 28.37 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
(Bank Active Mode: PRE + ACT + WRITE Commands,
Different Row Addresses, WTRCD = 0 Cycle, TRWL = 0 Cycle).................... 1447
Figure 28.38 Synchronous DRAM Auto-Refreshing Timing
(WTRP = 1 Cycle, WTRC = 3 Cycles) ............................................................... 1448
Figure 28.39 Synchronous DRAM Self-Refreshing Timing
(WTRP = 1 Cycle, WTRC = 3 Cycles) ............................................................... 1449
Figure 28.40 Synchronous DRAM Mode Register Write Timing (WTRP = 1 Cycle)............. 1450
Figure 28.41 PCMCIA Memory Card Interface Bus Timing ................................................... 1451
Figure 28.42 PCMCIA Memory Card Interface Bus Timing
(TED = 2.5 Cycles, TEH = 1.5 Cycles, One External Wait Cycle)..................... 1452
Figure 28.43 PCMCIA I/O Card Interface Bus Timing............................................................ 1453
Figure 28.44 PCMCIA I/O Card Interface Bus Timing
(TED = 2.5 Cycles, TEH = 1.5 Cycles, One External Wait Cycle)..................... 1454
Figure 28.45 DREQ Input Timing............................................................................................ 1455
Figure 28.46 MTU2 Input/Output Timing................................................................................ 1456
Figure 28.47 MTU2 Clock Input Timing ................................................................................. 1457
Figure 28.48 MTU2S Input/Output Timing ............................................................................. 1458
Figure 28.49 I/O Port Input/Output Timing.............................................................................. 1459
Figure 28.50 WDT Timing ....................................................................................................... 1460
Figure 28.51 Input Clock Timing ............................................................................................. 1461
Figure 28.52 SCI Input/Output Timing .................................................................................... 1462
Figure 28.53 Input Clock Timing ............................................................................................. 1463
Figure 28.54 SCIF Input/Output Timing .................................................................................. 1464
Figure 28.55 SSU Timing (Master, CPHS = 1) ........................................................................ 1466
Rev. 3.00 May 17, 2007 Page xliv of Iviii