SH7080 Datasheet, PDF (385/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
CK
A25 to A0
A12/A11*¹
CSn
RASL, RASU
CASL, CASU
RDWR
DQMxx
D31 to D0
BS
DACKn*²
Td1
Td2
Td3
Td4
Tp
Tpw
Tr
Tc1
Tc2
Tc3
Tc4
Tde
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.24 Burst Read Timing (Bank Active, Different Row Addresses)
Rev. 3.00 May 17, 2007 Page 327 of 1582
REJ09B0181-0300