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| SH7080 Datasheet, PDF (1485/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family | |||
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Section 28 Electrical Characteristics
Th
T1
Twx
T2
Tf
CK
tAD1
tAD1
A29 to A0
CSn
WRxx
RDWR
Read
RD
D31 to D0
tCSD
tWSD2
tRSD
tOE
tACC
tRWD
tRSD
tRDS1
tRDH1
tRWD
tCSD
tWSD2
tRWD
tRWD
RDWR
Write
D31 to D0
BS
DACKn*
TENDn*
tWDD1
tBSD
tDACD
tBSD
tWTH
tWTH
WAIT
tWTS
tWTS
Note: * The waveform for DACKn and TENDn is when active low is specified.
tWDH1
tDACD
Figure 28.17 Bus Cycle of SRAM with Byte Selection
(SW = 1 Cycle, HW = 1 Cycle, One External Wait Cycle, BAS = 1
(WE in Write Cycle Controlled))
Rev. 3.00 May 17, 2007 Page 1427 of 1582
REJ09B0181-0300
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