SH7080 Datasheet, PDF (835/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 15 Serial Communication Interface (SCI)
15.4.5 Multiprocessor Serial Data Transmission
Figure 15.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SCSSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SCSSR to 0 before transmission. All other SCI operations are the
same as those in asynchronous mode.
Initialization
[1]
Start transmission
Read TDRE flag in SCSSR
[2]
No
TDRE = 1?
Yes
Write transmit data to SCTDR and
set MPBT bit in SCSSR
Clear TDRE flag to 0
All data transmitted?
Yes
No
[3]
Read TEND flag in SCSSR
TEND = 1?
Yes
Break output?
Yes
Clear DR to 0
No
No
[4]
Clear TE bit in SCSCR to 0;
select the TXD pin
as an output port with the PFC
[1] SCI initialization:
Set the TXD pin using the PFC.
After the TE bit is set to 1, 1 is output
for one frame, and transmission is
enabled. However, data is not
transmitted.
[2] SCI status check and transmit data
write:
Read SCSSR and check that the
TDRE flag is set to 1, then write
transmit data to SCTDR. Set the
MPBT bit in SCSSR to 0 or 1. Finally,
clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to SCTDR, and then clear
the TDRE flag to 0. Checking and
clearing of the TDRE flag is automatic
when the DMAC or DTC is activated
by a transmit data empty interrupt
(TXI) request, and data is written to
SCTDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, first clear the port data
register (DR) to 0, then clear the TE
bit to 0 in SCSCR and use the PFC to
select the TXD pin as an output port.
<End>
Figure 15.16 Sample Multiprocessor Serial Transmission Flowchart
Rev. 3.00 May 17, 2007 Page 777 of 1582
REJ09B0181-0300