SH7080 Datasheet, PDF (530/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
• TSR2_0
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
-
- TGFF TGFE
Initial value: 1
1
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/(W)*¹ R/(W)*¹
Note: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Initial
Bit
Bit Name Value R/W
Description
7, 6 —
All 1
R
Reserved
These bits are always read as 1. The write value should
always be 1.
5 to 2 —
All 0
R
Reserved
1
TGFF
0
R/(W)*¹
These bits are always read as 0. The write value should
always be 0.
Compare Match Flag F
Status flag that indicates the occurrence of compare
match between TCNT_0 and TGRF_0.
[Setting condition]
• When TCNT_0 = TGRF_0 and TGRF_0 is
functioning as a compare register
[Clearing condition]
0
TGFE
0
• When 0 is written to TGFF after reading TGFF = 1*²
R/(W)*¹ Compare Match Flag E
Status flag that indicates the occurrence of compare
match between TCNT_0 and TGRE_0.
[Setting condition]
• When TCNT_0 = TGRE_0 and TGRE_0 is
functioning as compare register
[Clearing condition]
• When 0 is written to TGFE after reading TGFE = 1*²
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. If another flag setting condition occurs before writing 0 to the bit after reading it as 1, the
flag will not be cleared by writing 0 to it once. In this case, read the bit as 1 again and
write 0 to it.
Rev. 3.00 May 17, 2007 Page 472 of 1582
REJ09B0181-0300