SH7080 Datasheet, PDF (998/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 18 I²C Bus Interface 2 (I²C2)
18.6 Operation Using the DTC
In the I²C bus format, since the slave device or the direction of transfer is selected by the slave
address or the R/W bit, and the acknowledge bit may indicate the end of reception or reception of
the final frame, the continuous transfer of data by the DTC must be performed combined with the
CPU processing by the interrupt.
Table 18.5 shows some example of processing using the DTC. These examples assume that the
number of transfer data bytes is known in slave mode.
Table 18.5 Example of Processing Using DTC
Item
Master Transmit Master Receive Slave Transmit Slave Receive
Mode
Mode
Mode
Mode
Slave address +
R/W bit
transmission/
reception
Transmission by Transmission by Reception by CPU Reception by CPU
DTC (ICDR write) CPU (ICDR write) (ICDR read)
(ICDR read)
Dummy data read 
Processing by 

CPU (ICDR read)
Actual data
transmission/
reception
Transmission by Reception by DTC Transmission by Reception by DTC
DTC (ICDR write) (ICDR read)
DTC (ICDR write) (ICDR read)
Last frame
processing
Not necessary
Reception by CPU Not necessary
(ICDR read)
Reception by CPU
(ICDR read)
Setting of number
of DTC transfer
data frames
Transmission:
Reception: Actual
Actual data count data count
+ 1 (+ 1 equivalent
to slave address +
R/W bits)
Transmission:
Actual data count
Reception: Actual
data count
Rev. 3.00 May 17, 2007 Page 940 of 1582
REJ09B0181-0300