SH7080 Datasheet, PDF (199/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 7 User Break Controller (UBC)
Initial
Bit
Bit Name Value R/W Description
7
CDA1*
0
R/W L Bus Cycle/I Bus Cycle Select A
6
CDA0
0
R/W Select the L bus cycle or I bus cycle as the bus cycle of
the channel A break condition.
00: Condition comparison is not performed
01: The break condition is the L bus cycle
10: The break condition is the I bus cycle
11: The break condition is the L bus cycle
5
IDA1*
0
R/W Instruction Fetch/Data Access Select A
4
IDA0
0
R/W Select the instruction fetch cycle or data access cycle as
the bus cycle of the channel A break condition.
00: Condition comparison is not performed
01: The break condition is the instruction fetch cycle
10: The break condition is the data access cycle
11: The break condition is the instruction fetch cycle or
data access cycle
3
RWA1* 0
R/W Read/Write Select A
2
RWA0
0
R/W Select the read cycle or write cycle as the bus cycle of
the channel A break condition.
00: Condition comparison is not performed
01: The break condition is the read cycle
10: The break condition is the write cycle
11: The break condition is the read cycle or write cycle
1
SZA1*
0
R/W Operand Size Select A
0
SZA0*
0
R/W Select the operand size of the bus cycle for the channel
A break condition.
00: The break condition does not include operand size
01: The break condition is byte access
10: The break condition is word access
11: The break condition is longword access
Note: When specifying the operand size, specify the
size which matches the address boundary.
[Legend]
x:
Don't care.
Note: * These bits are reserved in the mask ROM and ROM-less versions. These bits are
always read as 0. The write value should always be 0.
Rev. 3.00 May 17, 2007 Page 141 of 1582
REJ09B0181-0300