SH7080 Datasheet, PDF (971/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 18 I²C Bus Interface 2 (I²C2)
Initial
Bit
Bit Name Value R/W Description
4
NAKIE
0
R/W NACK Receive Interrupt Enable
This bit enables or disables the NACK detection
interrupt request (IINAKI) and the overrun error (OVE
set in ICSR) interrupt request (IIERI) in the clock
synchronous format when the NACKF or AL/OVE bit in
ICSR is set. IINAKI can be canceled by clearing the
NACKF, AL/OVE, or NAKIE bit to 0.
0: NACK receive interrupt request (IINAKI) is disabled.
1: NACK receive interrupt request (IINAKI) is enabled.
3
STIE
0
R/W Stop Condition Detection Interrupt Enable
This bit enables or disables the stop condition detection
interrupt request (IISTPI) when the STOP bit in ICSR is
set.
0: Stop condition detection interrupt request (IISTPI) is
disabled.
1: Stop condition detection interrupt request (IISTPI) is
enabled.
2
ACKE
0
R/W Acknowledge Bit Judgment Select
0: The value of the receive acknowledge bit is ignored,
and continuous transfer is performed.
1: If the receive acknowledge bit is 1, continuous
transfer is halted.
1
ACKBR
0
R Receive Acknowledge
In transmit mode, this bit stores the acknowledge data
that are returned by the receive device. This bit cannot
be modified. This bit can be canceled by setting the
BBSY bit in ICCR2 to 1.
0: Receive acknowledge = 0
1: Receive acknowledge = 1
0
ACKBT
0
R/W Transmit Acknowledge
In receive mode, this bit specifies the bit to be sent at
the acknowledge timing.
0: 0 is sent at the acknowledge timing.
1: 1 is sent at the acknowledge timing.
Rev. 3.00 May 17, 2007 Page 913 of 1582
REJ09B0181-0300