SH7080 Datasheet, PDF (1628/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
Page Revision (See Manual for Details)
Table 28.7 Control Signal Timing 1415 Amended
Item
Symbol
Min.
MRES hold time
t_MRESH
15
MD1, MD0, FWE setup time
t_MDS
20
Figure 28.6 Reset Input Timing
Amended
Notes: 1. The RES, MRES, NMI, BREQ, and IRQ7 to
IRQ0 signals are asynchronous signals.
1416 Amended
MD1, MD0, FWE
MRES
tMDS
t_MRESS
t_MRESS
t_MRESW
Rev. 3.00 May 17, 2007 Page 1570 of 1582
REJ09B0181-0300