SH7080 Datasheet, PDF (213/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 7 User Break Controller (UBC)
7.3.12 Execution Times Break Register (BETR) (Only in F-ZTAT Version)
BETR is a 16-bit readable/writable register. When the execution-times break condition of channel
B is enabled, this register specifies the number of execution times to make the break. The
maximum number is 2¹² – 1 times. When a break condition is satisfied, it decreases BETR. A user
break interrupt is requested when the break condition is satisfied after BETR becomes H'0001.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
BET[11:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15 to 12 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
11 to 0 BET[11:0] All 0
R/W Number of Execution Times
Rev. 3.00 May 17, 2007 Page 155 of 1582
REJ09B0181-0300