SH7080 Datasheet, PDF (1019/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 19 A/D Converter (ADC)
• ADTSR_1
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TRG2S[3:0]
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R
R
R
R
R
R
R
R
R
R
R
R
Bit
Bit Name
15 to 12 TRG2S[3:0]
Initial
Value
0000
11 to 0 —
All 0
[Legend]
x:
Don't care
R/W Description
R/W A/D Trigger 2 Select 3 to 0
Select an external trigger, MTU2 trigger, or MTU2S
trigger to start A/D conversion for A/D module 2.
0000: External trigger pin (ADTRG) input
0001: TGRA input capture/compare match for each
MTU2 channel or TCNT_4 trough in
complementary PWM mode (TRGAN)
0010: MTU2 CH0 compare match (TRG0N)
0011: MTU2 A/D conversion start request delaying
(TRG4AN)
0100: MTU2 A/D conversion start request delaying
(TRG4BN)
0101: TGRA input capture/compare match for each
MTU2 channel or TCNT_4 trough in
complementary PWM mode (TRGAN)
0110: Setting prohibited
0111: MTU2S A/D conversion start request delaying
(TRG4AN)
1000: MTU2S A/D conversion start request delaying
(TRG4BN)
1001: Setting prohibited
101x: Setting prohibited
11xx: Setting prohibited
When switching the selector, first clear the ADST bit in
the A/D control register (ADCR) to 0.
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 May 17, 2007 Page 961 of 1582
REJ09B0181-0300