SH7080 Datasheet, PDF (477/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
10.4.6 Operation Timing
Figures 10.20 and 10.21 illustrate the timing of DMAC operations.
Clock (Bφ)
DMAC activation request
by DREQ pin
DMAC request
CSn
Internal address
R
W
Data transfer
Note: The DMAC request indicates the state of an internal bus request after determination of the source
for DMAC activation. For details on the DREQ and DACK timing in each operating mode, see
section 10.4.5, Number of Bus Cycle States and DREQ Pin Sampling Timing.
Figure 10.20 Example of Timing of DMAC Operation—Activation by DREQ
(in the Case of Cycle Stealing Transfer, Dual Address Mode, Low-Level Detection, Iφ:Bφ:Pφ
= 1:1/2:1/2, Data Transfer from External Memory to External Memory, and Idle/Wait = 0)
Rev. 3.00 May 17, 2007 Page 419 of 1582
REJ09B0181-0300