SH7080 Datasheet, PDF (181/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Interrupt Controller (INTC)
6.5 Interrupt Exception Handling Vector Table
Table 6.3 lists interrupt sources, their vector numbers, vector table address offsets, and interrupt
priorities.
Individual interrupt sources are allocated to different vector numbers and vector table address
offsets. Vector table addresses are calculated from the vector numbers and vector table address
offsets. For interrupt exception handling, the start address of the exception handling routine is
fetched from the vector table address in the vector table. For the details on calculation of vector
table addresses, see table 5.4 in section 5, Exception Handling.
IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0
and 15 for each pin or module by setting interrupt priority registers A to F and H to M (IPRA to
IPRF and IPRH to IPRM). However, when interrupt sources whose priority levels are allocated
with the same IPR are requested, the interrupt of the smaller vector number has priority. This
priority cannot be changed. Priority levels of IRQ interrupts and on-chip peripheral module
interrupts are initialized to level 0 at a power-on reset. If the same priority level is allocated to two
or more interrupt sources and interrupts from those sources occur simultaneously, they are
processed by the default priority order shown in table 6.3.
Rev. 3.00 May 17, 2007 Page 123 of 1582
REJ09B0181-0300