SH7080 Datasheet, PDF (1481/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

CK
A29 to A0
CSn
RDWR
RD
Read
D31 to D0
WRxx
Write
D31 to D0
BS
DACKn*, TENDn*
WAIT
T1
t_AD1
t_CSD
t_AS
t_CSS
Section 28 Electrical Characteristics
TwX
T2
t_AD1
t_CSD
t_RWD
t_RSD
t_ACC
t_OE
t_WSD1
t_WDD1
t_RWD
t_RSD
t_CSH
t_AH
t_RDS1
t_RDH1
t_WSD1
t_CSH
t_AH
t_WRH
t_WDH1
t_BSD
t_BSD
t_DACD
t_WTH
t_WTS
t_WTH
t_WTS
t_DACD
Note: * The waveform for DACKn and TENDn is when active low is specified.
Figure 28.13 Basic Bus Timing for Normal Space (One External Wait Cycle)
Rev. 3.00 May 17, 2007 Page 1423 of 1582
REJ09B0181-0300