SH7080 Datasheet, PDF (328/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Bit
6
5 to 0
Initial
Bit Name Value R/W Description
WM
0
R/W External Wait Mask Specification
Specifies whether or not the external wait input is valid.
The specification by this bit is valid even when the
number of access wait cycles is 0.
0: External wait is valid
1: External wait is ignored

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
(7) Burst ROM (Clock Synchronous)
• CS0WCR
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
BW[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
W[3:0]
WM
-
-
-
-
-
-
Initial value: 0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R/W R/W R/W R/W R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W Description
31 to 18 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
17, 16 BW[1:0] 00
R/W Number of Burst Wait Cycles
Specify the number of wait cycles to be inserted in the
second or subsequent access cycles in burst access.
00: 0 cycles
01: 1 cycle
10: 2 cycles
11: 3 cycles
Rev. 3.00 May 17, 2007 Page 270 of 1582
REJ09B0181-0300