SH7080 Datasheet, PDF (190/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Interrupt Controller (INTC)
6.8 Data Transfer with Interrupt Request Signals
The following data transfers can be done using interrupt request signals:
• Activate DMAC only; CPU interrupts do not occur
• Activate DTC only; CPU interrupts depend on DTC settings
Interrupt sources that are assigned for DMAC activation sources are masked without being input
to the INTC. The mask condition is as follows:
Mask condition = Interrupt source select (CH0) + interrupt source select (CH1) + interrupt source
select (CH2) + interrupt source select (CH3)
The INTC masks a CPU interrupt when the corresponding DTCE bit is 1. The conditions for
clearing DTCE and interrupt source flag are shown below.
DTCE clear condition = DTC transfer end • DTCECLR
Interrupt source flag clear condition = DTC transfer end • DTCECLR + DMAC transfer end
where DTCECLR = DISEL + counter 0
Figures 6.5 and 6.6 show control block diagrams.
IRQ edge detector
(in standby mode)
Standby cancel
determination
Standby control
IRQ pin
IRQ detection
Interrupt controller
Interrupt priority
determination
Interrupt request to CPU
DTCER
DTCE clear
IRQ flag clear by DTC
DTC
DTC activation
request
DTCECLR
Transfer end
Figure 6.5 IRQ Interrupt Control Block Diagram
Rev. 3.00 May 17, 2007 Page 132 of 1582
REJ09B0181-0300