SH7080 Datasheet, PDF (475/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
CK
Bus cycle
DREQ
(Overrun 0,
high-level)
DACK
(Active-high)
CK
CPU
CPU
1st acceptance
Non-sensitive period
DMAC
2nd acceptance
Acceptance
started
Bus cycle
DREQ
(Overrun 1,
high-level)
DACK
(Active-high)
CPU
CPU
1st acceptance
Non-sensitive period
DMAC
2nd acceptance
DMAC
3rd acceptance
Acceptance
started
Acceptance
started
Figure 10.17 Example of DREQ Input Detection in Burst Mode Level Detection
Figure 10.18 shows the TEND output timing.
CK
Bus cycle
DREQ
DMAC
End of DMA transfer
CPU
DMAC
CPU
CPU
DACK
TEND
Figure 10.18 DMA Transfer End Timing (in Cycle Steal Level Detection)
Rev. 3.00 May 17, 2007 Page 417 of 1582
REJ09B0181-0300