SH7080 Datasheet, PDF (369/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Bus State Controller (BSC)
Table 9.23 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0],
A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (4)-1
Setting
BSZ[1:0]
A2ROW[1:0]/ A2COL[1:0]/
A3ROW[1:0] A3COL[1:0]
10 (16 bits) 00 (11 bits)
00 (8 bits)
Output Pin of Row Address Column Address
This LSI
Output Cycle Output Cycle
SDRAM Pin
Function
A17
A25
A17
Unused
A16
A24
A16
A15
A23
A15
A14
A22
A14
A13
A21*²
A21*²
A12
A20*²
A20*²
A11
A19
L/H*¹
A12 (BA1)
A11 (BA0)
A10/AP
Specifies bank
Specifies
address/precharge
A10
A18
A10
A9
Address
A9
A17
A9
A8
A8
A16
A8
A7
A7
A15
A7
A6
A6
A14
A6
A5
A5
A13
A5
A4
A4
A12
A4
A3
A3
A11
A3
A2
A2
A10
A2
A1
A1
A9
A1
A0
A0
A8
A0
Unused
Example of connected memory
16-Mbit product (512 kwords × 16 bits × 2 banks, column 8 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
access mode.
2. Bank address specification
Rev. 3.00 May 17, 2007 Page 311 of 1582
REJ09B0181-0300