SH7080 Datasheet, PDF (848/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
• Four types of interrupts: Transmit-FIFO-data-empty, break, receive-FIFO-data-full, and
receive-error interrupts are requested independently.
• The transmit FIFO data empty and receive FIFO data full requests can activate the data
transfer controller (DTC) for data transfer.
• When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving
power.
• In asynchronous, on-chip modem control functions (RTS and CTS).
• The number of data in the transmit and receive FIFO registers and the number of receive errors
of the receive data in the receive FIFO register can be ascertained.
• A time-out error (DR) can be detected when receiving in asynchronous mode.
Figure 16.1 shows a block diagram of the SCIF.
Module data bus
SCFRDR
(16 stage)
RXD3
SCRSR
SCFTDR
(16 stage)
SCTSR
SCSMR
SCLSR
SCFDR
SCFCR
SCFSR
SCSCR
SCSPTR
SCBRRn
Baud rate
generator
TXD3
SCK3
Transmission/
reception
control
Parity generation
Parity check
Clock
External clock
CTS3
RTS3
[Legend]
SCRSR: Receive shift register
SCFRDR: Receive FIFO data register
SCTSR: Transmit shift register
SCFTDR: Transmit FIFO data register
SCSMR: Serial mode register
SCSCR: Serial control register
SCIF
SCFSR: Serial status register
SCBRR: Bit rate register
SCSPTR:Serial port register
SCFCR: FIFO control register
SCFDR: FIFO data count register
SCLSR: Line status register
Figure 16.1 Block Diagram of SCIF
Rev. 3.00 May 17, 2007 Page 790 of 1582
REJ09B0181-0300
Internal
data bus
Pφ
Pφ/4
Pφ/16
Pφ/64
TXIF
RXIF
ERIF
BRIF