SH7080 Datasheet, PDF (238/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Data Transfer Controller (DTC)
8.2.7 DTC Enable Registers A to E (DTCERA to DTCERE)
DTCER which is comprised of eight registers, DTCERA to DTCERE, is a register that specifies
DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is
shown in table 8.2.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DTCE15 DTCE14 DTCE13 DTCE12 DTCE11 DTCE10 DTCE9 DTCE8 DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15
DTCE15 0
14
DTCE14 0
13
DTCE13 0
12
DTCE12 0
11
DTCE11 0
10
DTCE10 0
9
DTCE9 0
8
DTCE8 0
7
DTCE7 0
6
DTCE6 0
R/W DTC Activation Enable 15 to 0
R/W ^{If set to 1, the corresponding interrupt source is specified}
as a DTC activation source.
R/W _{[Clearing conditions]}
R/W _{• Writing 0 to the bit after reading 1 from it}
R/W • When the DISEL bit is 1 and the data transfer has
R/W
ended
• When the specified number of transfers have ended
R/W
These bits are not cleared when the DISEL bit is 0 and
R/W _{the specified number of transfers have not ended}
R/W [Setting condition]
R/W ^{• Writing 1 to the bit after reading 0 from it}
5
DTCE5 0
R/W
4
DTCE4 0
R/W
3
DTCE3 0
R/W
2
DTCE2 0
R/W
1
DTCE1 0
R/W
0
DTCE0 0
R/W
Rev. 3.00 May 17, 2007 Page 180 of 1582
REJ09B0181-0300