SH7080 Datasheet, PDF (789/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 15 Serial Communication Interface (SCI)
15.3.6 Serial Control Register (SCSCR)
SCSCR is an 8-bit register that enables or disables SCI transmission/reception and interrupt
requests and selects the transmit/receive clock source. The CPU can always read and write to
SCSCR.
Bit: 7
TIE
Initial value: 0
R/W: R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
2
TEIE
0
R/W
1
0
CKE[1:0]
0
0
R/W R/W
Initial
Bit
Bit Name value R/W Description
7
TIE
0
R/W Transmit Interrupt Enable
Enables or disables a transmit-data-empty interrupt
(TXI) to be issued when the TDRE flag in the serial
status register (SCSSR) is set to 1 after serial transmit
data is sent from the transmit data register (SCTDR) to
the transmit shift register (SCTSR).
TXI can be canceled by clearing the TDRE flag to 0
after reading TDRE = 1 or by clearing the TIE bit to 0.
0: Transmit-data-empty interrupt request (TXI) is
disabled
1: Transmit-data-empty interrupt request (TXI) is
enabled
6
RIE
0
R/W Receive Interrupt Enable
Enables or disables a receive-data-full interrupt (RXI)
and a receive error interrupt (ERI) to be issued when
the RDRF flag in SCSSR is set to 1 after the serial data
received is transferred from the receive shift register
(SCRSR) to the receive data register (SCRDR).
RXI can be canceled by clearing the RDRF flag after
reading RDRF =1. ERI can be canceled by clearing the
FER, PER, or ORER flag to 0 after reading 1 from the
flag. Both RXI and ERI can also be canceled by
clearing the RIE bit to 0.
0: Receive-data-full interrupt (RXI) and receive-error
interrupt (ERI) requests are disabled
1: Receive-data-full interrupt (RXI) and receive-error
interrupt (ERI) requests are enabled
Rev. 3.00 May 17, 2007 Page 731 of 1582
REJ09B0181-0300