SH7080 Datasheet, PDF (908/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
16.5 SCIF Interrupt Sources and DTC
The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXIF), receive-error (ERIF),
receive-data-full (RXIF), and break (BRIF).
Table 16.16 shows the interrupt sources and their order of priority. The interrupt sources are
enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt
request is sent to the interrupt controller for each of these interrupt sources.
When TXIF request is enabled by TIE bit and the TDFE flag in the serial status register (SCFSR)
is set to 1, a TXIF interrupt request is generated.
When RXIF request is enabled by RIE bit and the RDF or DR flag in SCFSR is set to 1, an RXIF
interrupt request is generated. The RXIF interrupt request caused by DR flag is generated only in
asynchronous mode.
When BRIF request is enabled by RIE bit or REIE bit and the BRK flag in SCFSR or ORER flag
in SCLSR is set to 1, a BRIF interrupt request is generated.
When ERIF request is enabled by RIE bit or REIE bit and the ER flag in SCFCR is set to 1, an
ERIF interrupt request is generated.
When the RIE bit is set to 0 and the REIE bit is set to 1, SCIF request ERIF interrupt and BRIF
interrupt without requesting RXIF interrupt.
The TXIF interrupt indicates that transmit data can be written, and the RXIF interrupt indicates
that there is receive data in SCFRDR.
Table 16.16 SCIF Interrupt Sources
Interrupt
Source
ERIF
RXIF
BRIF
TXIF
Description
Interrupt
Enable Bit
Interrupt initiated by receive error (ER)
RIE or REIE
Interrupt initiated by receive data FIFO full (RDF) or RIE
data ready (DR)
Interrupt initiated by break (BRK) or overrun error RIE or REIE
(ORER)
Interrupt initiated by transmit FIFO data empty
TIE
(TDFE)
DTC
Activation
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Rev. 3.00 May 17, 2007 Page 850 of 1582
REJ09B0181-0300