SH7080 Datasheet, PDF (210/1644 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 7 User Break Controller (UBC)
Initial
Bit
Bit Name Value R/W Description
15
SCMFCA 0
R/W L Bus Cycle Condition Match Flag A
When the L bus cycle condition in the break conditions
set for channel A is satisfied, this flag is set to 1. In
order to clear this flag, write 0 into this bit.
0: The L bus cycle condition for channel A does not
match
1: The L bus cycle condition for channel A matches
14
SCMFCB 0
R/W L Bus Cycle Condition Match Flag B
When the L bus cycle condition in the break conditions
set for channel B is satisfied, this flag is set to 1. In
order to clear this flag, write 0 into this bit.
0: The L bus cycle condition for channel B does not
match
1: The L bus cycle condition for channel B matches
13
SCMFDA 0
R/W I Bus Cycle Condition Match Flag A
When the I bus cycle condition in the break conditions
set for channel A is satisfied, this flag is set to 1. In
order to clear this flag, write 0 into this bit.
0: The I bus cycle condition for channel A does not
match
1: The I bus cycle condition for channel A matches
12
SCMFDB 0
R/W I Bus Cycle Condition Match Flag B
When the I bus cycle condition in the break conditions
set for channel B is satisfied, this flag is set to 1. In
order to clear this flag, write 0 into this bit.
0: The I bus cycle condition for channel B does not
match
1: The I bus cycle condition for channel B matches
11
PCTE
0
R/W PC Trace Enable
0: Disables PC trace
1: Enables PC trace
Rev. 3.00 May 17, 2007 Page 152 of 1582
REJ09B0181-0300